This application is based on Japanese Patent Applications 2000-56201, filed on Mar. 1, 2000, and 2000-278587, filed on Sept. 13, 2000, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device and its manufacture method suitable for high integration of MISFET""s.
b) Description of the Related Art
A conventional manufacture method will be described which manufactures a semiconductor device with both logic circuits and dynamic random access memories (DRAM).
A gate lamination structure is first formed which is a lamination of a gate insulating film, a gate electrode and a silicon nitride film. By using the gate lamination structure as a mask, ions are implanted into active regions on both sides of the gate lamination structure to form low concentration regions of a lightly doped drain (LDD) structure. A side wall spacer of silicon oxide is then formed on the side wall of the gate lamination structure.
By using the side wall spacer as a mask, ions are implanted to form source/drain regions. Metal silicide films are formed on the surfaces of the source/drain regions of each transistor in the logic circuit area. A silicon nitride film is formed over the whole surface of the substrate, and an interlayer insulating film of silicon oxide is formed on the silicon nitride film. The silicon nitride film functions as an etching stopper when contact holes to the source/drain regions are formed.
Since the upper and side surfaces of the gate electrode are covered with the silicon nitride film, the gate electrode can be prevented from being exposed in contact holes formed through the interlayer insulating film of silicon oxide. The silicon nitride film exposed on the bottom of the contact hole is removed by phosphoric acid or the like. During this removal process, the side wall of the gate electrode is protected by the side wall spacer of silicon oxide. The silicon nitride film on the upper surface of the gate electrode is sufficiently thicker than the silicon nitride film exposed on the bottom of the contact hole. The upper surface of the gate electrode is not therefore exposed in the contact hole.
In this manner, the contact holes to the source/drain regions can be formed in a self-alignment manner.
As the space between gate electrodes becomes narrow linearly with an improved integration degree of DRAMs, an effective contact area of the source or drain region between gate electrodes becomes small being influenced by the thickness of side wall spacer and etching stopper silicon nitride film. A reduced contact area results in an increase in contact resistance. As the space between gate electrodes is made narrow by the side wall spacer and etching stopper silicon nitride film, it is difficult to fill the space between gate electrodes with an interlayer insulating film. As the space between gate electrodes is made still narrower, this space may be completely filled with the etching stopper silicon nitride film and the contact hole cannot be formed.
It is an object of the present invention to provide a semiconductor device and its manufacture method capable of filling an interlayer insulating film in a space between gate electrodes with good reproductivity even if the space is narrow.
It is another object of the present invention to provide a semiconductor device and its manufacture method capable of forming a contact hole in a region between gate electrodes with good reproductivity even if a space between gate electrodes is narrow.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; an element separation insulating film formed on a surface of the semiconductor substrate and defining first and second active regions: a first MISFET formed in the first active region and having a gate insulating film, a gate electrode, a source region, a drain region and a side wall spacer, the drain region of the first MISFET having a lightly doped drain structure with a low concentration region and a high concentration region, the low concentration region contacting the gate electrode as viewed along a substrate normal direction, and the side wall spacer conformingly covering a side wall of the gate electrode and a surface of the low concentration region in the drain region; a second MISFET formed in the second active region and having a gate insulating film, a gate electrode, a source region, a drain region and a side wall spacer, the side wall spacer of the second MISFET covering a side wall of the gate electrode and extending to surfaces of the source and drain regions; and an interlayer insulating film covering the first MISFET and second MISFET and being made of material having an etching resistance different from an etching resistance of the side wall spacers of the first MISFET and second MISFET.
The side wall spacer of the first MISFET is formed conformingly with a surface of underlying layer. Accordingly, as compared to the length of the low concentration region, the side wall spacer on the side wall of the gate electrode is thinner. As compared to the case where a side wall spacer having a thickness approximately equal to the length of the low concentration region is formed, a space between a gate electrode and an adjacent gate electrode or the like can be broadened. The side wall spacer of the second MISFET does not cover the upper the surfaces of the source and drain regions. Accordingly, a contact area between an upper wiring layer and the source/drain region via the contact hole can be broadened.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) forming an element separation insulating film on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film; (b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode; (c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask; (d) covering the first gate lamination structure with a first film made of insulating material; (e) forming a second film on the first film, the second film being made of insulating material having an etching resistance different from an etching resistance of the first film; (f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films; (g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask; (h) selectively removing the second film of the two layers constituting the first side wall spacer; (i) forming metal silicide films on surfaces of regions where the impurities were implanted by said implanting step (g); and j) forming an interlayer insulating film covering the first gate lamination structure and the metal silicide films.
Since the second film is selectively removed after the second impurity implanting step, the side wall spacer left on the side wall of the first gate lamination structure is made thin. The size of the impurity doped region by the first impurity implanting step is determined by the total thickness of the first and second films. By adjusting the thickness of the second film, the size of the impurity doped region by the first impurity implantation step can be controlled.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) forming an element separation insulating film made of silicon oxide on a surface of a semiconductor substrate to define a first active region surrounded by the element separation insulating film; (b) forming a first gate lamination structure on a partial surface area of the first active region, the first gate lamination structure including a gate insulating film and a gate electrode; (c) implanting impurities of a first conductivity type into surface layers of the semiconductor substrate on both sides of the first gate lamination structure, by using the first gate lamination structure as a mask; (d) covering the first gate lamination structure with a first film made of insulating material having an etching resistance different from an etching resistance of silicon oxide; (e) forming a second film made of silicon oxide on the first film; (f) anisotropically etching the second and first films to leave a first side wall spacer on a side wall of the first gate lamination structure, the first side wall spacer including at least two layers of the first and second films; (g) implanting impurities of the first conductivity type in surface layers of the semiconductor substrate, by using the first gate lamination structure and the first side wall spacer as a mask; (h) selectively removing the second film of the two layers constituting the first side wall spacer; (i) forming a metal silicide film on surfaces of regions where the impurities were implanted by said second impurity implanting step; and (j) forming an interlayer insulating film covering the first gate lamination structure and metal silicide films.
The etching speed of silicon oxide containing at least phosphorous or boron is faster than that of undoped silicon oxide. It is possible to reduce the etching amount of the surface of the element separation film while the second film is selectively removed.
As described above, the side wall spacer of the gate electrode of MISFET having the LDD structure is thin as compared with the length of the low concentration region. Gate electrodes can be disposed nearer to each other. The side wall spacer of MISFET without the LDD structure can be made thin without any restriction by the length of the low concentration region of MISFET with the LDD structure. An integration degree can therefore be improved.